1. Field of the Invention
The present invention generally relates to the design of integrated circuits and packaging for semiconductor chips, and more particularly to a method of modeling electromagnetic properties of a conductive plane in a layer of a chip or package.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
As the size of integrated circuits continues to shrink, and pin densities grow, it becomes increasingly more difficult to interconnect the chip to external circuitry. Chips are commonly attached to a substrate, e.g., a printed circuit board (PCB) using a socket or package which fans out the connections to pads or pins on the PCB. FIG. 1 illustrates a typical chip assembly which includes an IC chip 1, a package 2, a PCB 3, and miscellaneous components such as capacitors 4. These various elements may be electrically coupled using surface-mount connections with C4 solder ball arrays 5. IC chip 1 is connected to package 2 which is in turn connected to PCB 3. Package 2 and PCB 3 both have multiple horizontal layers interconnected by vertical vias. A single layer may contain multiple planes, i.e., some for wiring and others for an electrical ground plane or a power plane. A given plane in package 2 may have multiple connections to the top and bottom surfaces to couple ground or power planes of IC chip 1 to ground or power planes of PCB 3. It is common to find 24 or more levels of wiring within a package.
The package itself can significantly affect the performance of the integrated circuit it supports, particularly as power supply currents, power densities, and operating frequencies increase. It is accordingly important to understand how the electromagnetic properties of the package design will impact the chip assembly. Hardware failures can occur due to, e.g., an inadequate package power grid which cannot be detected with existing package verification procedures. Standardized measurement techniques are difficult to apply to the wide variety of systems that use different application-specific integrated circuits (ASICs) which require a large number of custom IC packages.
There are generally two types of IC packages, ceramic and organic (polymeric). Ceramic packages generally require wider wires, resulting in lower wiring density and more layers. Organic packages can provide narrower wires (with higher wiring density and fewer layers) and are generally less expensive to make. Consequently, organic packages are widely used with ASIC chips. Organic packages, however, tend to have more irregularly-shaped planes and wiring. Although the difficulties of package verification apply to both ceramic and organic packages, these difficulties are exacerbated by the irregular metal planes more commonly found in organic packages.
FIG. 2A depicts an example of an irregular metal plane 6 that might be used in an organic package. The conductive plane has various cutouts to accommodate wiring or pads and holes for mounting or vias. The cutouts and holes are placed at non-uniform locations around the plane, making it very difficult to use simple models for current flow. One approach to simulating irregular planes is to divide up the conductive area into a multitude of rectangles which are then considered as discrete elements of a resistive network. FIG. 2B shows one way that the plane 6 of FIG. 2A could be formed into a grid of rectangles. An integral equation can then be used to derive equivalent circuits, as discussed in the article “Equivalent Circuit Models for Three-Dimensional Multiconductor Systems,” by A. Ruehli (IEEE Transactions on Microwave Theory and Techniques, vol. MTT-22, no. 3, pp. 216-221, March 1974). These models, referred to as partial element equivalent circuits (PEEC), provide for the calculation of partial inductances and partial capacitances between adjacent rectangles by establishing segments between adjacent nodes for capacitance (C-segments) and inductance (L-segments). L-segments are separately computed for the two orthogonal directions x and y (capacitance is a scalar value, but inductance is a vector since it depends upon the direction of current flow).
Analysis of a conductive plane using rectangulation offers many benefits. Electromagnetic couplings can be evaluated much more quickly using formulas for capacitance and inductance, and if the number of parameters are limited then efficient hashing can be used to reduce repetitious coupling calculations. There are, however, still some problems with this approach. Current techniques for verifying organic packages require manual gridding of the planes because of their irregular shapes. Manual gridding is both inefficient and error-prone. Furthermore, while the PEEC technique is easy to implement for simple (uniform) rectangular arrays, it is much more difficult when the rectangles are not aligned or are of different sizes. In the most straightforward scenario, where all rectangles are equal and aligned in a neat grid, the circuit can be modeled by placing circuit nodes at the center of the rectangles. The C-segments simply correspond to the rectangle shape, and are assigned the locations of the nodes (one node per C-segment). The Lx-segments and Ly-segments are the same size as the C-segments but are offset from the C-segments by half a grid spacing, i.e., half the rectangle length or width. For example, a grid of four uniform rectangles placed in a 2×2 configuration will have four C-segments (overlapping the respective rectangles), two Lx-segments (one between the two nodes in the upper row, and one between the two nodes in the lower row), and two Ly-segments (one between the two nodes in the left column, and one between the two nodes in the right column).
As the grid pattern becomes more irregular, this simple segment model becomes unworkable since the nodes are not collinear. For rectangles that are aligned but of unequal sizes, the rectangles are conventionally modeled with circuit nodes assigned to each of four corners of a rectangle, rather than the center. This type of grid is usually derived from recursive bisectioning. A C-segment is assigned to each of the four corner nodes, with a size that is one-fourth that of the rectangle. Lx-segments and Ly-segments are centered about the edges (boundaries) of adjacent rectangles. This model results in just slightly more than one node per C-segment.
For the most irregular grids, where rectangles are both unaligned and unequal, circuit nodes can again be placed at the corners, and the Lx-segments and Ly-segments are similarly centered about the edges of adjacent rectangles. This technique is used by the field solver program known as “FastHenry,” described in the FAQ (frequently asked questions) at Internet web page http://www.fastfieldsolvers.com/faq.htm. FastHenry computes the frequency-dependent self and mutual inductances, as well as the resistances, of a generic tridimensional conductive structure. An input file describes the geometry, i.e., the coordinates which specify every rectangular conductor as a sequence of rectilinear segments connected between nodes (points in 3D space).
This model results in much more than one node per C-segment, due to the edge-based Lx- and Ly-segmentation when creating RLC lumped circuits. The increased number of circuit nodes (and segments) creates a significant delay in the circuit simulation and analysis. A typical ASIC package may have as many as 200,000 nodes, which presents a considerable computational challenge. It would, therefore, be desirable to provide a fast and comprehensive analysis framework to better understand the electromagnetic properties of metal planes and predict package effects. It would be further advantageous if the modeling method could utilize more efficient automation techniques.